Constant writing rate character generation and display system

ABSTRACT

A character generator in which strokes are generated to form characters wherein each stroke is treated as a vector whose end points are stored digitally. The characters are formed from a variable number of strokes which are of varying periodicity such that a constant writing speed is obtained regardless of the number of strokes required per character; the time for writing a particular stroke is proportional to the stroke length. Two sets of digital to analog converters sum analog signal outputs in two channels such that digital control signals are loaded into the digital to analog converters alternately while X and Y axis beam steering and appropriate blanking and unblanking signals are employed for stroke writing.

United States Patent I OFFSQET' OFFSET CONTROL Bryden 1 Nov. 7, 1972 I[54] CONSTANT WRITING RATE 3,474,439 I I D/1969 Miners"; ..340/324 ACHARACTER GENERATION AND v DISPLAY SYSTEM 7 Primary Examiner-John W.Caldwell I Assistant Examiner-Marshall M. Curtis [72] Inventor: JosephBryan Frammgham Attorney-Milton D. Bartlett, Joseph D. Pannone, Mass- I'4 v I Herbert W; Arnold and David M. Warren 4 73 Ass nee: Ra theon Cornan Lexin on, I l 1 lg Ma ss. p y [571 ABSTRACT- [22] Filed; Sept 30,1970 A character generator in which strokes are generated to formcharacters wherein each stroke is treated as a [21] PP 76,912 vectorwhose endpoints are stored digitally. The f 1 characters are formed froma variable number of 52 U.s. Cl. .340/324 A, 320/1 strokest'which are ofvarying Periodicity such that a 51 Int Cl ..G06t3/14' Writing speed isObtained regardless of the [58] Fig." 340/324 320/] number of strokesrequired per character; the time for v writing a particular strokeisproportional to the stroke length. Two sets of digital to'analogconverters sum [56] References analog signal outputs in two channelssuch that digital UNITED. STATES PATENTS control signals'are loaded intothe digital to analog converters alternately while X and Y axis beamsteer- 3'325'802 2 Bacon ing and appropriate blanking and unblankingsignals A 3:296,609 1/1967 Wilhelmsen 340/324 A 5 Claims, 8 DrawingFigures 's fl I xggmggo SIGNAL 36 1/2 TRANSLA I20 EVEN 'X D/A /2aMULTIPLIER SIZE TRIANGLE AMPLIFIER X OUTPUT GENERATOR D/A PLIE 32 $24CLAMP CLOCK D/A EVEN Y GENERATOR PUER 30 000 EVEN CLOCK IFIER OUTPUT D/AMULTIPLIER BLANK/ UNBLANKING CONTROL P'A'TENTEDNHT' 7 m2 A 3-.702.4 70

SHEET 1 (IF 5 /8 I CHARACTER /4 GENERATOR A T B LOCAL a LOCAP VECTOR h rBUFFER MEMORY GENERATOR i I POSITION CENTRAL l GENERATOR AIR COMPUTERTRAFF|C Q- DATA I i 2a /30 5 36 i CHARACTER I GENERATOR EL; f LOCALLOCAL g VECTOR BUFFER T MEMORY GENERATOR\ 32 DISPLAY v POSITIONGENERATOR Rf t +V 'f(t)) EVEN u 532 TO D/A v f(T)+v v flL) MULTIPLIERS.

TO OTHER 602 v STAGES V, /4 BIT INPUT 5-- P'A'TENTEDnuv 11912 sum 2 or 5I X CHANNEL TIME FIG. '2,

FIG. 3

eousrsnrrwnrrructnxrnenamcrrnn g tGE-NERA IQNANH BP. SY

BAQ GR UND oarrriiNvaNnoN j This; inventionrelates; to:-,afconstant;-speed gcharact'er generator in r-whichkcha'racters aredeveloped f from a ,plurality of generated -.strokes';rwhichimay he ad-.vantageously lutilizeda in' zhigh datadensity=display,' such -asareusediniairtraffic controlsystems. t

, RInorder'to.-achieve';.highrefficiency in a cathode ray,

-.-tube., display. orstrok'e,;generator, it is important-that thewriting speedzbe maintained substantially constant and that the blank,beam l'ostitime gis minimizedi These criteria i are satisfied in acharacter -generator" in acicordance with the tpr'inciples of -theapresent invention :byselectingl a writing-timewhich.iscloselyproportional to;the.writtenlineilength of thecharacterto be written.

, :suMM av OFTHE INVENTION stroke ,-generator for] charactert-genera'ti'on is described in which 'azvariable numberlof'strokesisutilizedin; thez generation of characters for visual display.:Thetimeduration of individual strokes is" variable and {proportional tothe. stroke length such that constant -writing-spe edis'maintainedregardless of-the numberof stroke s'per character orthestrokelength. This variable :periodicity of f the :generatedstrokes? isobtained in a combined digital and analog system in which segment 7 zperiodicity data, segment end pointdata, timing and The character-iscomposed of Iamumber-of @sectors'bf varying number and length :inaccordance with the .characterdetail. Theltotalitime required to writeagpar- =ticular character is maintained the :same regardless of thenumber :of strokes or the length :of ithe "strokes required :thereforeby varying the segment tperiodicity,

or thetimeirequired fdr-thegeneration of:the particularstroke'orsegment.

' Aproblem of the prior artiscumulativelossiof-accuracy which occurswhen the-end positions of seg- .ments are connected to form characters.The present invention -;uses a technique of combining positive and vnegative going ramps 'of different amplitudes in idem, .cal time periodsto define the itwo end positions and all intermediatepositions. Therequired amplitude is obtained byamultiplying digital :to analogconverter co'ntrolled :by data-in :bit form obtained from read onlymemory. The advantage of using digital to analog converters to controlthe magnitudeiof the input-ramp is that large lquantities of digitalwords may be stored in i extremely compact devices. Furthermore, thisselection ofv characters isobtained directly ffromthe digital numbersand no analog switching is required.

' ln systemsfof the prior art constant writing speedcould only beobtained by the use of complex and costly brightness control circuitrysince the writing timeiis not porportional to the written line length insuchfsystems. L

In another system of the prior art a beam current in a cathode raytube'displayis generated porportional to a control signal'definingthelength'of the vectorto be generated, thus, the intensity of 'the beamcurrent is controlled as a function of the beam velocity to afford auniform display intensity irrespective of the length or of the velocityof the vector, Howeyer, in such systems zunblanking-. data are digitallygenerated and suppliedto analog character generation circuitry. TheIratesupply ing'new digital wor'dszis "slow relativefto the rate at-whichthe-datais clocked intofthe analogcircuitry.

The digital signals received bythe analog circuitry lproduce coordinated'X and Y channel waveforms and a blank/unblank signal to control thebeam of a cathode ray tube to display cursive ly written charactersi Thebeam-on to beam offtime ratio'is maximized by generating justtherequired numberof segments for 'any'particular character, and-writingwithsubstantially a constantspeed. A widera'nge'of'seg'ment lengthisobtainablesucht'hata single segment is used for a straight lineregardless ofits' le'ngth. Referencing is-provided to either-thecenteroracorner of thecharacter.

. Two triangular waveforms are generated "to form a bipolar output whichis summed-to obtain a "resultant waveform which isa ramp connecting thesegment end :points. A .novel triangle generator is described in which apositive or a negative voltage is developed depending upon whether apositive or negative ramp analog out- ;put is required. The value ofcurrent from selected positive and negative current sources isdeterminative of' the segment periodicity and is controlled digitallyfroma read only memory- The current sources are operative alternately,and duringinoperative periods,

data is'received tochange the triangle generator outputto1digitaltoanalogniultipliersto thevalue required for the generation ofthe next-segment.

The triangle generator after amplification drives four digitalto analogmultiplierswhich operate in pairs with their multiplying factor beingcontrolled by a digital input and changeable only when there is zeroanalog in- .put. Thus, the digital word to the digital-to-analogmultipliers is clocked in at alternate segment periods. For

example, while one multiplier of a pair is generating an odd" segment,the register of the other multiplier of complex intensity controlcircuitry is required and variably periodicity is not provided.

" In other systems of the prior art'the current required for strokegeneration is proportional to the velocity of the specific embodiment inwhich the characters are formed from a plurality of individual strokesand which i used in connection with an air traffis 9m system, it is tobe understood that the techniquesof the present 1 the stroke. While acharacter generator is described in invention couldapply equally w ellto other systems requiring a constant speed-character generator of highaccuracy. L .With constant writing speed it':

:unblank' the beam and nbbrigh'tnss compensation signals are required'for the cathode ray tube.

is only necessary to the pair is receiving new digital data for thegeneration of the next segment, or the evensegment; which is clocked inas the analog signal passes through zero.

BRIEF DESCRIPTION OF THE DRAWlNGS ofFlG. 2.

cordance withthepresent invention.

' FIG. 8 is a circuit diagram of a digital to analog multiplier inaccordance with the principles of the present invention. I DESCRIPTIONOF THE PREFERRED EMBODIMENT Referring now to FIG. 1 a block diagramof anair traffic control system embodying the present invention isillustrated generally at 10. Data from air terminals at variouslocations such as weather conditions, flight patdescribed with referenceto FIG. 5. Toobtain constant writing speed, the periodicity of theramps'must be present invention is shown generally at 100. A size andtern information, aircraft position and other data normally utilized byair controllers is inputted to a central computer '12'over a pluralityof data channels A, B N at which point the data is stored and theappropriate information is relayed to the local airterminals and air.

controller points such as 14 where a local buffer interface transfersthe appropriate data to a local memory 16 which supplies positional,character and vector information to a' character generator 18, a vectorgenerator 20 and a positional generator 22 in accordance with thepresent invention. Vector generator 20 may be of conventional design asis the position generator 22 for controlling the deflection of theelectron display beam of display 24 which may comprise a cathode raytube. Other aircraft control points may be supplied in a similar fashionwith a local buffer 26 receiving data in a parallel channel from thecentral computer 12 for transfer to a local memory 28 into theassociated character generator 30, vectorgenerator 32 and positiongenerator 34 for the. control of characters and vector-information onadisplay 36. I I

Referring now to FIGS. 2 and 3, the principle of character generationemployed by the present invention is illustrated. Two triangularwaveforms, V fU) and V (l-flt)) are multiplied by a gain function i'ndigital to analog multipliers 50 and '52 respectively and varied, andthe'condition forconstant writing speed is that (6X 5Y*)/'(3T is aconstant, where ST is the period-.oftransition for 8X and BY. The SK and6Y are.

the "deflection increments as scaledat "the display screen; The periodof transitionjs determined by a seven-bit word that is predetermined andstored in a digital memory. Of course, the number of bits determinative'of the transition may be any amount desired. A-n unblankingbit is alsostored in the digital memory in order to allow common formats forcharacters to be chosen which may be stored with'the digital. words. The

digital word may effectively consist of five bits for X,

five bits for Y, seven hits representative of time and three bits forunblanking for a total of 20 bits for each line segment. The three bitsfor unblanking allows choice of three unblanking sequences for a singlewriting pattern. I I I v g Referring now to FIG. 4 a block diagramof theanalog portion of the character generator of the offset voltage controlis inputted to a character size voltage generating circuit 102 and acharacter offset voltage generating circuit 104 for developing V and Vrespectively. A triangle generator 106 generates triangular pulsesofconstant peak to peak amplitude with changing periodicity as isdescribed with reference to FIG. 6. Thisseries of triangular pulses isgenerated only when an unclamping, signal inputted, to the trianglegenerator via line 108 is low, otherwise no triangular output isgenerated. The clamping control is described I with reference to FIG. 6.The amplitude of the generated triangular waveforms is determined by Vwith the slope of the positive going ramp determined by a seven-bitcontrol signal received from a stroke segment memory via line 1 10 atdigital to analog converter summed in a summing network 54. Digitalinputs containing stroke end point data are applied to the digital toanalog multipliers 50 and 52 via data lines 56 and S8 respectively.Waveform Vgflt) is shown as A in FIGS."2 and 3 and is one input for theX channel of the stroke generator. Wavefonn V (l--f(t)) is shown as B inFIGS. 2 and 3 and is the other input for the X channel of thestroke'generator. The outputs of the digitalto analog multipliers 50 and 52 areshown as A and B. The resultant R- is a ramp connecting the endpointswhich are determined 'by the multiplying factor;

As is apparent from FIG. 3, the amplitude of R, at the beginning and endof each segment isdeterrnined by the gain factors of the :digital toanalog multipliers 50 and '52 with the A and B channels alternatelyproviding the end point values. The gain factors are controlled by 112which is coupled to'a positive constantcurrent sourcein the trianglegenerator while the slope of the negative goingramp is likewisecontrolled by a sevenbit control signal inputted via line 116 to adigital to analog converter 114 which is coupled to a negative constantcurrent sourcein the triangle generator control signal 116.

- A phase inverter 500 develops two phases of the triangular pulses asis described with reference to FIG. 7 and is capable of driving fourdigital to analog multiplier 120, 122, 124 and 126 of the type describedwith respect to FIG. 8. Digital to analog multipliers through 126 eachrequire five data bits to control the signal attenuation in a simpleladder network. The outputs of each pair of multipliers are summed attheinputs to line amplifiers 128 and 130. The outputs of line amplifiers128 and 130 are the drive signals supplied to the X and Y axesrespectively of the character display. The offset voltage V,,developed'in offset generator 104 proportionalto the size of thecharacter and to the character size voltage V is also added to the lineamplitier's 128 and 130.

A comparator in the triangle generator 400 produces a square wave whichis negative during the period of positive going ramps and zero, duringthe period of negative going ramps. This waveform is used to controlgates for selecting the two phase blank/unblank signals obtained fromthe digital memory described 'with clock pulses from the risingedge ofthesqua'rew'ave which are .coupled'to the D/ih'multiplierstoithe digitaltimingand. control logic. These 'clock pulses' cause the digital signalsX and. Y to be loaded'into the live bit D/A multip iers 20 thr ieh mia da also used to 1 activatethe digital'logicand memories. 1

. v The unblankingsignal is selected at unblanking gates at amplifier13.4 from a" digital control signal from the digital timing and control'logicand is amplified in the unblanking line amplifier 134.,Dotunblanking isobtained from a. monoshot circuit ,in'thetiming and controllogic {fed to the unblank gates? g The digi al to analog'ml ltipliers120 through 1 126 operate in pairs and are fedjfrom the two phaseoutputs from the phaseinverter 5.00.1t will be'obseryed thatthemultiplying factor controlled byfthe digitalinput to the digital toanalog multipliers'is only changed when its analog input is at zero, inother words, the multipliers a e t d l in t ha seda th c mmsm ms wfalternate segment periods, hence-the terminology odd andevenX and :Yinputs to the BIA multipliersIThus, when a five bitsignal is 'beingclockedthroughfa D/A multiplier after translation insignal translator136, the other five-bit signalis being inputted to the other D/Amultiplier for the same axis. The'outputs of each pair of multipliersare summed in a resistance network and amplified to drive a75ohmunbalanced lin v a R r i g n t G- 5 ls' d s al'p flion 9f h charactergenerator is illustrated generally at 200. Timing'and control logic inthe digital circuitry generates suitable clock pulses for unloading aread-only segment memory in whichthe; various stroke data is stored intothe digital to analog converters in a timing sequence. Additionally,-the timing and control logic serves .to count the. number. of segmentwords for comparison with the number of words allocated for. anyparticular character and is automatically reset when that number hasbeen reached..When reset, new characters may be generated upon receiptof load and start signals by the control logic. r

Data in the form of a six bit character codeplus pari ty enters thesystem "through the input logic shown generally at 202 which includesconventional shift registers 204 and the character address and controlfor a segment memory from which various control signals are derived aswill be explained. In addition to the character code, size and offsetcontrol signals are received by a character code register 204, which areinverted by inverters 206 and Y208 with the. inverted signals'b'eingsupplied to the analog size and offset circuitry described withreference to FIG. ,4. t o I A parity bit is received in a conventionalmanner at a parity checking circuit 210 of conventioiial 'design. Ifparity is correct, the six bit character code-and the size and offsetsignals, which are treated as data, are loaded into the charactercodere'gister 204 in accordance with 1* .6 is resetIto-all zeros. Evenand .odd parity is imparted to the timing -andcontrol logic via lines214 and 216 respectively, with the-appropriate clearingsignal beingreceived-via line 21.8 from the timing andcontrol logic 220 at thecharacter code-register.

The character codeis imputted to a read only startingaddre'ss andcontrol memory .222'via line 2241if parity is correct. Memory 222 isformed of integrated circuit logic modules of conventional design, andmay beconsidered to be a codetranslator that permits the association ofany starting address for-the stroke segment memory with anysix-ibitcharacter code. Thus,

where the input character code is standard ASCII, memory222 provides anaddress to the initial word in the segment memory, data'specifying thenumber of segment .words in the selected character, the location 1 ofthe desired two 'bit (blanking) within the segment word, and data todistinguish between normal cursively written characters, a dot,andu'nused character codes.

' Memory 222 is continuouslyaccessed by the character, code register 204which supplies an enabling [signal in addition to the character, code.The memory portionof address and control circuitry222 effectivelycomprises four 256-bit memory chips of 64 words, each of 16-bit length.A common format occurs when the same portions of the segment memory areused for the generation of different characters, for example, thevertical line present in an.E,-an F,and-an l... Y

.1 The output portion'of the startingaddress and control memorycomprises-four four-bit MSl generalpurpose Y registers which maybeloaded simultaneously withone word fromthe memoryfor each character tobaccessed f Y I a The segment memory 230 is a read only memory thatcontainsall the data necessary to display the complete compliment ofcursively written characters as well as a parity error symbol. The"segment memory is divided into six blocks of 32 words each giving atotal capacity of 1 92 words, with each word defining two20-bit-segments. The number of words per character format may vary,for:example'=, from one to eight with the present coding but may be aslarge as 16. While theoretically a format could be placed anywherewithin the memory, in actual practice the'format location is limited toa single l6'-,wordsecti on so thatonly thefour least significant bits"of the address received on line 232 from the segment memory addressregister 234 are required to change during the display of a singlecharacter.

While the present design provides 41 formats including the parity errorsymbol it is to be understood that the memory may be expanded as desiredin accordance with cor'iyentional integrated circuit techniques merelyby adding additional memory circuit modules. For the displayof a givencharacter the starting address and control memory 222 supplies thesegment memory address register 234 with an eight-bit starting address.The register 234 is: a down-counter which .then proceeds to count downsequentially until it is commanded to clear to all zeroes by the timingand control logic 220 via the clear segment memory address re- "'gisterline 236 JSincethere'is a logic inversion in each Thethree mostsignificantbits of the comp'let'e'address are decoded in anaddressdecoder 238 and'inputted via line 240 to enable one of the six blocks oftli'e segment memory. The reset word is located at the final address ofthe first block of the segment memory and 1 under normal operation thesegment memory'will segment, each of which -bit half words comprisesfive bits to specify the horizontal or X end point of the segment, fivebits to specify the vertical orY end point of the segment, seven bitstospecify a time number denoting the time duration of the segment andthree bits, one for each of three possible characters within a format tospecify whether the segment is blanked (a logical one) or unblanked (alogical zero) with the latter three bits being the blanking bits, or 2bits.

Both halves of the memory output word are loaded into the'segement datamemoryregisters at the same time. The segments however are processedsequentially through the rest of the circuitry with the first segmentbeing the odd segment and the second segment being the even segment. Theformat may contain an odd or an even number of segments, if desired,while the second half of the last memory word isthe same asthe resetword. Z-bit, or blanking location information stored in the startingaddress and control memory 222 is loaded into the operation controlregister 242 in,

response to a loading signal online 244 from the timing and controllogic. This blanking or Z-bit control is inputted on -line'246 to the Zbit selection'circuit 248 which is an MSI logical unit that performsadual selection of a'pair (odd and even) of Z-bits from the sin Z- bitsin the segment memory output supplied to. the Z-bit selector 248 on dataline 250; The control signal online 246 comprises two bits which havethe same value for all the words in ony character format. The outputs ofthe Z-bit selection logical unit 248 are cconnected to segment dataregisters 262and 264 of the output registers shown generally at 260 aswill be explained; Timing signals are receivedby the word count register266 from the control logic 220 on line268 and each zero count isreceived by the timing logic on line 270. The timing signals necessaryfor dot generation are received by the operation control register 242via line 272 and dot command signals are inputted to the timing andcontrol from the operation control register 242 via lines 274 and 276. v

The output registers 260 or the segment data registers, consist of l lfour-bit MSI shift registers. Five of these registers shownrepresentatively as 280 are loaded in parallelwith ten odd and ten evenbits of X and Y end point data, five bits for X, and five bits for Y,withthe odd segment bits alternating with the even'segmentbits. Datalines 282 and 284 from the segment memory couple ten-bit outputs whichare alternate physical locations of the stroke end point data toregisters 2 80 andare connected directly tothe analog circuitry asdescribed with reference to FIG. 4 via lines 286'arid 288 where they arereceived at the appropriate time by either of two odd br even high speedregisters. The outputsof registers 280 will contain the odd seg'-' 8ment data immediately after the segment data registers have "been loadedfrom the segment memory output were! At the next step in-the operatingsequence registers 280 will receive a shift clock pulse from thetimingand control logic 220 vialine 290 which causes the evehsegmemdata't'o appear on the ten output lines. Froin'then on data lines 286and 288 to the analog circuitrywill altemate with oddand even segmentsuntil a reset from the segmentmemory is loaded in response to a clocksignal from the timing and controlling logic via line 292. Lines 286 and288 which represent the segmerit end pointswill then remain-at a logicalzero until the next character is processed. Since I there is no masterclear it is necessary' to process at least one character after powerturn on to arrive at the above logical zero condition.

SixMSI registers illustratively shown as registers 262, 264, and 294each of which comprisestwo registers, are used to process the timeperiods and blankingdata received via 'lines 296 and 250 respectively 2(seven for time and one for blanking) corresponding to the odd segmenteight bits corresponding to the even segment. The eight outputs fromregisters .264 which contains the odd segment data'are connecteddirectly to the analog circuitry via line 298. The eight outputs fromregisters 262 and 294containing the even segment time and blanking dataare coupled to the analog circuitry via line 30.0.

The even Z bit is inverted by inverter 302 before it is loaded intoregister 294. The first set of-two'registers, 262 for the evensegmentdata is labeled A registers while thesecond set-294 is labeled-Bregisters. The 2- bit .output from the B registers is connected via aninverting gate (not shown) in the timing and controllogic 220-to theanalog circuitry while theother seven bits of the B register areconnected directly to the analog circuitry. The even segment datalinesto the analog circuitry are changed at alternate intervals from theodd segment data lines. to the analog circuitry, however, both remainsteady for two segmentperiods. At the end of the display for one symbol,the segment time period lines 298 and 300 for the odd segment period andeven segment periods respectively will remain at logical zero while theblanking lines 304 for odd blanking and 188 for even blanking willremain at logical one. This logical one condition of the blanking linesin the case of the odd segment data results from the reset word fromsegment memory 230 while in the case of the even segment data thecontents of the even B registers 294 are either that of the last memoryword to be used in the character format when the total number ofsegments in the character is odd or that of the reset order when thetotal number of segments is even.

The timing and control logic 220 of the digital module provides all theclock signals and control levels required to implement the operationspreviously prescribe'd.This logic is the source of all the timing pulsesrequired by the digital module which together with theodd clock and theeven clock input lines from the 9 analog circuitry determine the:order-and time duration of th'evarious operations required'ijn additionthis logic unclamps and clampsthe analogfcircuits, controlsunblankingand providesvarious-indications onthe data console. Thetiming-and control logic comprises conventional MSl logicmodules. Clampsignalsare applied to the analog circuitry-vialine-306lwith dot'blankingon .line 308'-.which:the odd andievenxclocksare-receivedon lines;3-10and3l2 respectively. Varioussignals'from the central "computer are also-'received bythe timing and'control logic, such as enabling signals fordata loading, and a central clock if desired-on line 314,316

and Y318. An. end of character signal is coupled on line 320 to theanalogcircuit.

Referring how 01 16.6 the trianglegenerator is' shown generally at .400.The triangular waveform generator 400 and thegphase inverter 500generate-two while transistor "428 Y is on and transistorv 428 switchesoff whiletransistor 430 ison in order that currentloadingfromthepositive andnegative current sources 404 and 406respectively to the'comparator is kept-approximatelyconstant. The voltagefacross thecapacitor 402 :is :amplifiedand'phase inverted to provide the two,phases' required by the BIA multipliers as described with reference to-FIG. 4. The triangle waveform generatorsupplies both the X and Y D/Amultipliers 120 through 1:26and the triangle waveform is phaseinvertedand referenceto V to minimize transients when V is changed byvarying the character size with the voltage V addedto the supply voltageB-i-Q A-clamp circuit indicated: generally at 440 arrests'the action ofthe triangular waveform generator on completion of a character whichholds the voltage across capacitor 402 at zero under the command ofphases of triangular pulsesof constant peak amplitude but with changinglperiodicity. i In the triangular waveform generator, a capacitor "402is charged from either a positive or negative constant current source404 or 406:respectively. The choice of source depends upon whetherapositive or negative slope is required. A differential circuit in acomparator 408alternately compares the voltage across capacitor 402 withzero volts andwith the peak positive value V QThis com- I parator 408switches "the constanteurrent' sources 404 and 406 such that when thevoltage across capacitor 402 starts at zero the positive constantcurrent source 1404 is operative and'the capacitor is charged until thecomparator detectsthe value as being equal-to Y at which. point thepositive. current source .is then switched off and the negative currentsource 406 is switched on.;Capacitor 402 is then discharged to zero .andthe whole cycle recommences'z- 402 to vary between zero and V); and isset by the seven-bit digital to analog converters and controlled'vialines 298 and 300 by the even segment period-and the odd segment period.data :from registers300 and-.298 respectively of theoutput registers ofthe digital circuitry. Since only one ,gonstant current source-isoperative at a time, during the inoperative periods it is possibletochange the'inputto the seven-bit digital to'analog converters to thevalue ,requiredfor the next-segment. The alternate inputs zero and Vsupplied tothe comparator 408 are switched bya switching transistor4l2.The voltage across the charging capacitor .402 is large compared witheither V or zer'o'a Thus, if compared with zero this voltage must benegative and if compared with V it must be positive. The transistorpairs 4 14 and 416-and 418 and 420 are differentially "connected to formthe comparator while transistor 422 acts as the positive current sourceand transistor 424 as anegative current source. v t The peak positivevoltage V f-is amplified by an emitter follower transistor 326 prior tocomparison in comparator 409 Signal translation from the capacitor lQtI'Ol signals from thetiming and control logic 220 I received at 442.Diodes 4,44 and 446 act asrestraining diodes for the clamp circuit, theoutput'of which is of course applied to the capacitor -402-.-Transistors448 and 450 form a differential amplifier, the output of which iscoupled through emitter'follower452 to clamp the emitter voltageoftransistor 2454. Five-volt outputs are providedat the collectors oftransistors 454 and 456 respectively, a supply voltage isprovided at458, and a potentiometer (not shown) providea clamp level control at460. Tr'ansistors462 and 4614; provide signal translation for thereference outputs to the positive Y- bit -D/A converter at 466, 468and'f470 while reference output tothe negative seven-bit D/A converterare provided by aconnection totheemitter of transistors 424 81111432 andtapsacross a zenerdiode 472 at 474, 476 and ,478-respectively.Transistor-480 and zener diode .482 provide biasingifor the comparator408. A negative 11.4 volts is supplied at 484. I, -Referring now to FIG.7 the-phase inverter is shown generally at 500. The peak signalamplitude or dc size control .V,; which is a function of time is aunipolar signalinputted to the base of transistor .502 on line 504. Asupply voltage which may effectively be 24 volts is applied throughresistor 506 byan emitter follower circuit 508 through thecollector oftransistor 502 while I the negative supply voltage is applied throughresistor 5 l0tothe emitter of transistor 502 thereby producing abipolaroutput on lines 512 and 514 with V f,(t)+V on line 512 and +V f(t)+Vonline 514 with V being the dcoffset-voltage. Capacitors 5-16 and 518allow dc isolation to permit the triangular waveforms to be dorestoredgto new reference leads, V and zero. Diode emitter followers 528and 530 respectively to provide an even segment triangle voltageoutputon line 532 to the even D/A converters and an odd segment trianglevoltageoutputon line 534 to the odd D/A converters.

Referringnow to-FIG. 8 aportion of a typical digital to analogmultiplier of the present invention capable of accepting a-single bit ofdata is illustrated generally at 600. The digital to analog multipliersoperate in pairs as described with reference to FIG. 4 and are fed fromthe two phaseoutputs, on lines 532 and 534 from the phase ll inverter500. The multiplying factor of theD/A multiplier is controlled by adigital input, and; is only changed when its analog input is at zero. In,other words, the multipliers have the digital input changed at thebeginning of alternate segment periods. Theout- I puts of each pair ofmultipliers are summed in a resistance ladder network 630 and amplifiedto drive a 7'5-ohm funbalanced line. FIG. 8 is illustrative of the .,bysaid ramp generation means by one of said r v digital-control signals ofsaid storage means for linear transistor pair of switches 618 and 620,which In the character generator described, X, Y, blanking,

and period data are all digitally stored; however, this data could ofcourse first be received on a communication line before local storage.

While particular embodiments of the invention have been shown anddescribed, various modifications thereof will be apparent to thoseskilled in the art and therefore it is not intended that the inventionbe limited to the disclosed embodiments or to details thereof and 3departures may be made therefrom within the spirit and scope of theinvention as defined in the appended claims.

What is claimed is: i l. A character generation system comprising:

7 means for generating a ramp function signal, said generation meansproviding a positive ramp function and a negative ramp function, saidgeneration means being responsive to digital control signals of astorage means for controlling the temporal duration of each of said rampsignals such that each of said durations is predetermined in accordancewith said digital control signals;

means for storing said digital control signals, said storage means beingresponsive to a computer supplied address for selecting a set of suchdigital con- .trol signals corresponding to a selected character whichis to be generated;

first means for multiplying a ramp signal generated scaling said rampsignal; means for complementing a ramp said ramp generation means; v

Qsecond means, coupled to said complementing means, for multiplying saidcomplemented ramp signal by a second, one of said digital controlsignals of said storage means for sealing said comme aiii s f o i' rii iriiri g aii cl scaled ramp signals of said first and said secondmultiplying means to provide the instantaneous value of a coordinate ofa segment of said selected character; t a means coupled to saidcombining means andresponsive to said coordinate for displaying saidcharacter; and i I said ramp generation means signaling said storagemeans to update the values of respectiveones of said control signals tosaid first and said second multiplying means when each of said scaledramp signals of respectively said first and said second multiplyingmeans has a zero value, successive ones of said coordinates therebybeing provided such that one coordinate is initiated immediately upontermination of a preceding coordinate. 2. The system according to :claim1 wherein said signal provided by ramp generation means comprises acapacitor and a pair of current source means for charging anddischarging said capacitor, each of said current source means providingfor a continuously variable duration of said ramp signals in response tosaid control signals of said storage means.

3.- The system according to claim 2 wherein said ramp generation meanscomprises comparator means for comparing the magnitude of said rampsignal to a reference signal, said comparator means terminating suchramp signalwhen said value of said ramp signal equals the value of saidreference signal, and means for varying said reference signal inresponse to one of said control signals of said storage means to providea continuously variable maximum amplitude to said ramp signals.

4. The system according to claim 2 further comprising means forcomputing air traffic control data, said computing means processing saiddata to provide a format for said data wherein said data appears in twoportions, one of said portions being suitable to be applied as a controlsignal to said first multiplying means and said second portion beingsuitable to be applied as said digital control signal to said secondmultiplying means, 5. The system according to claim 2 further comprisingmeans responsive to said control signal of said reference and coupled tosaid combining means for off-

1. A character generation system comprising: means for generating a rampfunction signal, said generation means providing a positive rampfunction and a negative ramp function, said generation means beingresponsive to digital control signals of a storage means for controllingthe temporal duration of each of said ramp signals such that each ofsaid durations is predetermined in accordance with said digital controlsignals; means for storing said digital control signals, said storagemeans being responsive to a computer supplied address for selecting aset of such digital control signals corresponding to a selectedcharacter which is to be generated; first means for multiplying a rampsignal generated by said ramp generation means by one of said digitalcontrol signals of said storage means for scaling said ramp signal;means for complementing a ramp signal provided by said ramp generationmeans; second means, coupled to said complementing means, formultiplying said complemented ramp signal by a second one of saiddigital control signals of said storage means for scaling saidcomplemented ramp signal; means for combining said scaled ramp signalsof said first and said second multiplying means to provide theinstantaneous value of a coordinate of a segment of said selectedcharacter; means coupled to said combining means and responsive to saidcoordinate for displaying said character; and said ramp generation meanssignaling said storage means to update the values of respective ones ofsaid control signals to said first and said second multiplying meanswhen each of said scaled ramp signals of respectively said first andsaid second multiplying means has a zero value, successive ones of saidcoordinates thereby being provided such that one coordinate is initiatedimmediately upon termination of a preceding coordinate.
 2. The systemaccording to claim 1 wherein said ramp generation means comprises acapacitor and a pair of current sourcE means for charging anddischarging said capacitor, each of said current source means providingfor a continuously variable duration of said ramp signals in response tosaid control signals of said storage means.
 3. The system according toclaim 2 wherein said ramp generation means comprises comparator meansfor comparing the magnitude of said ramp signal to a reference signal,said comparator means terminating such ramp signal when said value ofsaid ramp signal equals the value of said reference signal, and meansfor varying said reference signal in response to one of said controlsignals of said storage means to provide a continuously variable maximumamplitude to said ramp signals.
 4. The system according to claim 2further comprising means for computing air traffic control data, saidcomputing means processing said data to provide a format for said datawherein said data appears in two portions, one of said portions beingsuitable to be applied as a control signal to said first multiplyingmeans and said second portion being suitable to be applied as saiddigital control signal to said second multiplying means.
 5. The systemaccording to claim 2 further comprising means responsive to said controlsignal of said reference and coupled to said combining means foroffsetting the center of a displayed character.